Analysis of Low Frequency Drain Current Model for Silicon Nanowire Gate-All-Around Field Effect Transistor

This paper is investigated the low frequency noise behavior in subthreshold regime of gate-all-around silicon nanowire field effect transistors. Downscaling of multi gate structure beyond 50 nm gate length describes the quantum confinement related model. A drain current model has been described for output characteristics of silicon nanowire FET that is incorporated with velocity saturation effects and compact modeling of RF noise behavior is analyzed for gate-all-around structure. Noise performance of gate-all-around transistor is investigated at high frequency band for radio frequency RF specified application and consequently low frequency noise behavior can be analyzed using drain current model. This paper shows that noise is decreasing with frequency. Higher subthreshold, lower drain induced barrier lowering DIBL, higher on-off ratio and higher noise figure at lower frequency is achieved by gate all around configuration and comparison has been done with double gate structure.